1. Field of the Invention
The present invention relates to a method of growing embedded compressive and a tensile strain-inducing materials in source/drain (S/D) regions of a p-type field effect transistor, p-FET, and an n-type field effect transistor, n-FET, respectively, of a complementary metal oxide semiconductor (CMOS) circuit in a gate first flow for manufacture. In particular, the method uses a reactive ion etch (RIE) to form recesses within the S/D regions of the transistors of the CMOS circuit for successive epitaxial growths of the two embedded strain-inducing materials. More particularly, the CMOS circuit includes a gate wire between extending from a gate of an n-FET, over an isolation region, to a gate of a p-FET.
2. Description of the Related Art
Numerous performance and economic advantages have been achieved by the scaling of semiconductor devices to smaller dimensions. For example, the scaling of metal oxide semiconductor field effect transistors (MOSFETs) has lead to shorter channel lengths, increased switching speeds, and greater circuit densities.
Scaling transistors to smaller dimensions is limited by characteristics of the transistor's performance. For example, shorter channel lengths of smaller dimensioned transistors can produce undesired variability of threshold voltages and increased drain leakage currents. One means of improving transistor performance for transistors showing such short channel effects is to introduce an appropriate mechanical stress into source/drain (S/D) regions that surround a channel of a transistor. It is known that a compressive stress induced in the channel of a p-FET by, for example, a proximate silicon germanium (SiGe) layer, will enhance majority charge carrier mobility within the p-FET's channel, and thus, enhance the p-FET's performance, and that a tensile stress, induced in the channel of an n-FET by, for example, a proximate silicon carbon (SiC) layer, will enhance majority charge carrier mobility within the n-FET's channel, and thus, enhance the n-FET's performance. It is also known that an embedded layer of a strain-inducing material, i.e., a layer formed coplanar to or below the surface of the substrate, can produce larger stresses on the channel of a transistor, when compared to a layer of the same strain inducing material formed above the surface of the substrate.
Typically, when strain-inducing materials are introduced into the S/D regions proximate to the channels of n-FET and p-FET transistors in a gate first flow for the manufacture of a CMOS circuit, two separate processes are used. A first process may include: depositing a first protective layer over both n-FET and p-FET regions of the CMOS circuit, each transistor region including a gate stack formed on a substrate and S/D regions formed within the substrate; forming a first hard mask over the n-FET region; a first reactive ion etch to remove the first protective layer over the p-FET region and to form recesses within the S/D regions adjacent to the p-FET gate stack; and epitaxially growing SiGe within the recesses adjacent to the p-FET gate stack. Subsequently, the first hard mask covering the n-FET region is removed and a second process follows. The second process may include: depositing a second protective layer over both the n-FET and p-FET regions of the CMOS circuit, each transistor region including a gate stack formed on a substrate and S/D regions formed within the substrate; a second reactive ion etch to remove the second protective layer over the n-FET region and to form recesses within the S/D regions adjacent to the n-FET gate stack; and epitaxially growing SiC within the recesses adjacent to the n-FET gate stack. Subsequently, the second S/D mask covering the n-FET region is removed. Thus, the two separate processes include depositing a first protective layer over both the n-FET and p-FET regions, a first reactive ion etch to remove a portion of the first protective layer that covers the n-FET region, depositing a second protective layer over both the n-FET and p-FET regions, and a second reactive ion etch to remove a portion of the second protective layer that covers the p-FET region.
A gate wire is a basic component of CMOS circuits and is formed by a “wire” of gate material, for example, polysilicon, that includes a gate of an n-FET transistor at one end of the wire, a gate of a p-FET transistor at the other end of the wire, and gate material extending between the n-FET gate and the p-FET gate. In an area located between the n-FET and p-FET regions, the gate wire overlies a substrate of insulating material, which electrically isolates the n-FET region from the p-FET region. A gate wire is used, for example, at the input of a CMOS inverter circuit.
Manufacturing a CMOS circuit that includes a gate wire is problematic, when the two separate processes for introducing strain-inducing materials into S/D regions of n-FET and p-FET transistors in a gate first flow are used. The two processes include formation of a first hard mask over the first protective layer in the n-FET region and of a second hard mask over the second protective layer in the p-FET region. Subsequently, each of the protective layers is removed by first and second reactive ion etches over transistor regions not covered by a hard mask. However, with small dimensions, for example, CMOS transistors of 22 nanometer node technology or smaller, the probability of a misalignment of a few nanometers in the placement of the first hard mask and the second hard mask at a junction between the n-FET and the p-FET regions is significant. It has been shown that misalignment of the two hard masks can result in CMOS circuit defects, caused by either non-overlap or overlap of the protective layers deposited on a gate wire disposed between the n-FET and the p-FET regions.
Referring to FIG. 1A, a top view shows a misalignment of two non-overlapping hard masks 102, 104 relative to a portion of a gate wire 105 disposed between n-FET and p-FET S/D regions 106, 108, respectively, in a CMOS circuit formed by a gate first flow, while FIG. 1B shows a transverse section of a portion of the CMOS circuit through a transverse section line A-A of the gate wire 105 in FIG. 1A. In FIG. 1A, the first hard mask 102 of the first process covers a portion of a first protective layer (not shown) including the n-FET S/D region 106. A first reactive ion etch removes the remaining portion of the first protective layer not covered by the first hard mask 102, including a non-overlap region disposed between the n-FET and p-FET S/D regions 106, 108. Etching the first protective layer in the non-overlap region, however, exposes the underlying gate wire 105. The first hard mask 102 is then removed. The second hard mask 104 of the second process covers a portion of the second protective layer (not shown) including the p-FET S/D region 108. A second reactive ion etch removes the remaining portion of the second protective layer not covered by the second hard mask 104, including the non-overlap region. However, etching the second protective layer in the non-overlap region also exposes the underlying gate wire 105.
Referring to FIG. 1B, a first protective layer 112 is disposed over the gate of the n-FET S/D region 106, i.e., the left-end of gate wire 105, that had been masked by the first hard mask 102, while the second protective layer 114 is disposed over the gate of the p-FET S/D region 108, i.e., the right-end of gate wire 105, that had been masked by the second hard mask 104. The gate wire 105, however, is exposed in the non-overlap region created by the two non-overlapping hard masks 102, 104. In the exposed non-overlap region, epitaxial growth of a strain-inducing material, meant to fill the recesses etched in the S/D regions of the transistors adjacent to their gate stacks, can occur on the exposed polysilicon gate material and cause defects in a subsequent silicidation process in the manufacture of the CMOS circuit.
Referring to FIG. 2A, a top view shows a misalignment of two overlapping hard masks 202, 204 on a portion of a gate wire 205 formed disposed between n-FET and p-FET S/D regions 206, 208, respectively, in a CMOS circuit, while FIG. 2B shows a transverse section of the portion of the CMOS circuit through the transverse section line A-A of the gate wire 205 in FIG. 2A. In FIG. 2A, the first hard mask 202 of the first process covers a portion of the first protective layer (not shown) including the n-FET S/D region 206 and an overlap region, which comprises a portion of the first protective layer to be subsequently covered by the second hard mask. A first reactive ion etch removes the remaining portion of the first protective layer not covered by the first hard mask 202. The second hard mask 204 of the second process covers a portion of a second protective layer (not shown) including the p-FET S/D region 208 and the overlap region, upon which the first protective layer has been deposited. A second reactive ion etch removes the remaining portion of the second protective layer not covered by the second hard mask 204. When the second hard mask 204 is removed, the second protective layer is disposed on that portion of the layer, which was covered by the second hard mask, and over the first protective layer, which had been deposited on the overlap region. That is, the overlap region is covered by both the first and second protective layers.
Referring to FIG. 2B, a first protective layer 212 is disposed over the gate, i.e., the left-end of the gate wire 105 of the n-FET 106 region, and the overlap region that had been masked by the first hard mask 102, while a second protective layer 214 is disposed over the gate, i.e., the right-end of the gate wire 105 of the p-FET S/D region 108, and the overlap region that had been masked by the second hard mask 104. Hence, the gate wire 105 is covered by two overlapping first and second protective layers in the overlap region. The increased thickness of the two overlapping protective layers, relative to the thickness of the one protective layer over each of the n-FET and p-FET gates, becomes problematic when the gate wire 105 is to be subsequently silicided both at the overlap region, which is a common junction for the gate inputs of a CMOS inverter, and over the individual n-FET and p-FET gates of the CMOS circuit. In a robust process to remove the relatively thicker overlapping first and second protective layers from the gate wire 105 in the overlap region, the relatively thinner protective layer over each of the n-FET and p-FET gates is subject to silicide-gate electrical shorts, caused by removing sidewalls of the n-FET and p-FET gate stacks.
There remains a need for an efficient and economical method of manufacturing a CMOS circuit of small dimensions in a gate first flow that prevents the problems, described above, in a method including epitaxial growth of strain-inducing materials in S/D regions of an n-FET and p-FET connected by a gate wire.